1. Field of the Invention
The present invention generally relates to a method of making a semiconductor device and, more particularly, to a method of making a resin encapsulated semi conductor device that is designed to eliminate peeling and/or separation of an insulating layer which tends to occur adjacent and around an area where a circuit conductor is formed.
2. Description of the Prior Art
In a semiconductor device such as, for example, a GaAsMMIC, including a high power amplifier, a low-noise amplifier, an analog and/or digital circuit or the like, plating lines are often employed as a connecting conductor (an air-bridge interconnect or a cross-over conductor) between electrical component parts such as inductors, resistors, capacitors, internal matching circuits and/or bonding pads and also as a lead line for connecting a bonding pad with, for example, a terminal pin.
FIG. 8 illustrates schematically such a semiconductor device as viewed from the top. The illustrated semiconductor device comprises a semi-conductor chip 1 including a plurality of bonding pads 3 connected through connecting conductors 2 with circuit elements in an electrical circuit comprised of, for example, field-effect transistors, inductors, resistors and/or capacitors. A known version of this semiconductor device is shown in a cross-sectional representation in FIG. 9 taken along the line 1X--1X in FIG. 8 and is fabricated according to the sequence shown in FIGS. 10A to 10D. In the discussion that follows, reference will be made to a single bonding pad 3, situated in a pad area A, and an electrical connection between this bonding pad 3 and one of the field effect transistors situated in a FET area B.
In making the prior art semiconductor device shown in FIGS. 8 and 9, as far as the FET area B is concerned, an active layer 11 of the field effect transistor is formed on the semiconductor substrate 10 by an ion implantation technique as shown in FIG. 10A and, after ohmic electrodes 12 and gate electrodes 13 have been formed on the active layer 11, the field effect transistor is connected with active elements by means of transmission lines 20. After deposition of an insulating material on the semiconductor substrate 10 to form insulating films 40, a portion of each insulating film 40 is removed to provide contact areas 41.
On the other hand, as far as the pad area A is concerned, an insulating material is deposited on the semiconductor substrate 10 to form an insulating film 40, after a transmission line 20 has been deposited on the semiconductor substrate 10, to enhance bonding of the insulating film 40 with the semiconductor substrate 10, followed by removal of a portion of the insulating film 40 to provide a contact area 41.
Each of the contact areas 41 has an overlap structure wherein the associated insulating film 40 overlaps the transmission line 20 in a distance generally within the range of 0.5 to 2 .mu.m.
Then, as shown in FIG. 10B, a first level photoresist layer 300 is formed over the insulating film 40 with local portions of the first level photoresist layer 300 removed in alignment with the respective contact areas 41 in a size larger than the opening of each contact area 41 and smaller than the width of the associated transmission line 20. After deposition of the first level photoresist layer 300, a conducting layer 30 is formed over the first level photoresist layer 300 by a sputtering technique.
After deposition of the conducting layer 30 over the first level photoresist layer 300, a second level photoresist layer 310 is formed over the first level photoresist layer 300 as shown in FIG. 10C, with local portions of the second level photoresist layer 310 removed in alignment with the respective contact areas 41 in a size larger than the corresponding depleted area in the first level photoresist layer 300, then aligned with the respective contact area 41.
Thereafter, as shown in FIG. 10D, the assembly is subjected to an electroforming process wherein an electrically conductive material such as, for example, Au is plated selectively only on portions of the conducting layer 30 which are exposed through respective openings in the second level photoresist layer 310 to form a plating layer 31, followed by removal of the photoresist layers 300 and 310 and the conducting layer 30 to leave a plating line 32 as shown in FIG. 9. The resultant assembly is finally resin encapsulated to complete the semiconductor device.
The semiconductor device so formed has the plating line 32 adjoining the insulating film 40 as shown in FIG. 9. Where the semiconductor chip is packaged by encapsulating it with an inexpensive resinous material, the adjacent insulating film 40 is needed to have a thickness not smaller than 1.5 .mu.m to avoid any possible penetration of moisture into the semiconductor substrate through the resinous package. However, it has been found that the plating line 32 formed according to the prior art method generally has an internal stress tending to urge the adjacent insulating film 40 and, accordingly, the use of the increased thickness of the insulating film 40 results in increase of the area of contact between the plating line 32 and the insulating film 40. The increase of the area of contact between the plating line 32 and the insulating film 40 is problematic in that in the event that the amount of stresses transmitted from the plating line 32 to the insulating film 40 exceeds a critical value, the insulating film 40 tends to be peeled off and/or separate from the semiconductor substrate 10 as indicated by 4 in FIGS. 11A and 11B the latter figure being a cross-section of FIG. 11A taken along line XIB--XIB.
Since the areas of separation 4 of the insulating film generally occur between the semiconductor substrate 10 and the insulating film 40, not only are surface areas of the semiconductor substrate 10 exposed to the outside, but also the active elements disposed adjacent the areas of the separation 4 tend be adversely affected, accompanied by a reduction in operating characteristics and reliability of the electrical component parts.